Latest Publications
- Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, Virendra Singh, “A High Performance
Scan Flip-Flop Design for Serial and Mixed Mode Scan Test”, IEEE Transaction on Device and
Materials Reliability (TDMR), 18 (2), 321-331, 2018.
- Darshit Vaghani, Satyadev Ahlawat, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh,
"On Securing Scan Design Through Test Vector Encryption”, IEEE International Symposium
on Circuits and Systems (ISCAS) 2018, Florence, Italy, May 27-30, 2018, pp. 1-5.
- Satyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu, Virendra Singh, “On Securing Scan
Design from Scan-Based Side-Channel Attacks”, 26th IEEE Asian Test Symposium (ATS),
Taipei, Taiwan, November 27-30, 2017, pp. 58-63.
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Binod Kumar, Ankit Jindal, Jaynarayan Tudu, Brajesh Pandey, Virendra Singh, “Revising Random
Access Scan for Effective Enhancement of Post-silicon Observability”, 23 rd IEEE International
Symposium on On-Line Testing and Robust System Design (IOLTS), Thessaloniki, Greece, July
3-5, 2017, pp. 132-137.
- Jaynarayan Tudu, “JSCAN: A Joint-scan DFT Architecture to Minimize Test Time, Data Volume,
and Test Power”, 20th IEEE International Symposium on VLSI Design and
Test (VDAT) 2016, Guwahati, India, May 24-27, 2016, pp. 1-6.
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